The invention generally relates to semiconductor memory devices and more particularly to a nonvolatile semiconductor memory cell with electron trapping and methods for operating the same.
Memory devices for nonvolatile storage of information are in widespread use in the art. Exemplary nonvolatile semiconductor memory devices include read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and flash EEPROM.
Flash EEPROMs are similar to EEPROMs in that memory cells can be programmed (i.e., written) and erased electrically but with the additional capability of erasing all memory cells at once. The widespread use of EEPROM semiconductor memory has prompted much research focusing on developing an EEPROM memory cell with optimal performance characteristics such as shorter programming times, lower voltage usage for programming and reading, longer data retention time, shorter erase time and smaller physical dimensions.
FIG. 1 is a block diagram that illustrates the structure of a prior art nonvolatile memory cell where a nonvolatile memory cell 70 includes an N-channel MOSFET structure. The nonvolatile memory cell 70 includes a P type substrate 706 with two buried N+ junctions, one being the source 700 and the other being the drain 701. A channel 707 is formed between the source 700 and the drain 701. Above the channel is a first isolating layer 703, which generally is a silicon oxide layer. On top of the first isolating layer 703 is a trapping layer 704, which generally is a nitride layer. The trapping layer 704 forms the memory retention layer that traps the hot electrons as they are injected into the nitride layer. A second isolating layer 705, which generally is an oxide layer, is formed to overlay the silicon nitride layer. The silicon oxide layer 705 electrically isolates a conductive gate 702 formed over the second isolating layer 705. The two silicon oxide layers 703 and 705 function as isolation dielectric layers.
This prior art structure can provide a two-bit cell, i.e., the nonvolatile memory cell can store two bits of data. The memory is programmed by channel hot electron injection. By applying programming voltages to the gate 702 and the drain 701 while the source 700 is grounded, electrons can be accelerated sufficiently to be injected into the trapping layer 704 near the drain side 701 so as to increase the energy barrier in the channel 707 near the drain side 701 where a bit of data is stored therein. In addition, electrons can be injected into the trapping layer 704 near the source side 702 to increase the energy barrier in the channel 707 near the source side 701 where another bit of data is stored therein. Provided that the trapping layer 704 includes an appropriate width, the two areas storing electrons in the trapping layer 704 can be identified and used for storing two bits of data.
Regarding the energy barrier of the prior art nonvolatile memory cell, the trapping layer is in a neutral state. When no charge is stored in the trapping layer, the energy barrier in the channel 707 is at a low state. In programming the nonvolatile memory cell, the electrons are injected into the trapping layer near, e.g., the drain 701, so that the energy barrier in the channel 707 near the drain 701 is increased. Moreover, when the electrons are injected into the trapping layer 704 near the source 700, the energy barrier in the channel 707 near the source 700 is increased. The energy barrier in the channel 707 thus includes two high-level sections distributed at two sides of the energy barrier.
Conventional programming using hot electron injection requires high operating voltages and consumes high power. As the size of the nonvolatile cell is reduced and the channel is relatively small, the high operating voltage induces a punch-through effect resulting in high leakage current and low program efficiency. Such becomes a significant design and implementation shortcoming in prior art nonvolatile memory devices serving as two-bit memory cells. Further, the prior art structure requires a particularly confined size, which impedes engineering efforts on size and cost reduction therefor.
Thus, there is a general need in the art for a nonvolatile memory device with an optimal two-bit cell structure, and more particularly, a nonvolatile memory device and associated methods therefor that overcome at least the aforementioned disadvantages of nonvolatile memory devices in the art. In particular, there is a need in the art for a nonvolatile memory device with amplified effects for the trapped electron charges in the trapping dielectric layer and an optimally reduced size.
A preferred embodiment of the invention provides a trapping nonvolatile memory cell comprising a P type semiconductor substrate, a source which is a buried N+ junction area, a drain spaced from the source which is also a buried N+ junction area, a channel being formed in a space between the source and the drain and within the semiconductor substrate, a first isolating layer overlying and covering the channel, a nonconducting charge trapping layer formed on and overlaying the first isolating layer, a second isolating layer formed on and overlaying the nonconducting charge trapping layer, a gate comprising an electrically conductive material formed on and overlaying the second isolating layer.
In this particular embodiment of the nonvolatile memory cell structure according to the invention, the nonconducting charge trapping layer is formed so as to receive and retain electrons injected to the nonconducting charge trapping layer in a first charge storage region close to the drain for storing digital data, and a second charge storage region close to the source. For the erase state in operating the nonvolatile memory according to the invention, electrons are stored in the nonconducting charge trapping layer. In programming the nonvolatile memory according to the invention, electric holes are injected into the nonconducting charge trapping layer. Moreover, a tunneling layer can be added between the channel and the first isolating layer so as to reduce the injecting energy barrier from the channel to the trapping layer wherein the electrons and holes are readily injected into the trapping layer in the operation mode.
The invention further provides a method for programming one bit in a trapping nonvolatile memory cell in accordance with the invention. An embodiment of the method according to the invention comprises the steps of applying a first voltage difference between a selected electrode of the source and the drain and the gate, where the first voltage difference is small enough to cut off a charge flow from the selected electrode to the gate so that no current flow occurs therebetween, and applying a second voltage difference between the gate and a second electrode of the source and the drain, where the second voltage difference is large enough to form an electric field that induces a current along a path from the second electrode to the trapping layer. Moreover, two bits can be programmed at generally the same time by applying the second voltage difference to the source and drain in a generally simultaneous manner.
The invention further provides a method for reading one bit in a trapping nonvolatile memory cell. An embodiment of the method according to the invention comprises the steps of applying a first voltage difference between a selected electrode of the source and the drain and the gate, where the first voltage difference is large enough to turn on the selected electrode and the gate, and grounding a second electrode of the source and the drain, where the bit state on the side of the second electrode is accordingly read and output.
In addition, the invention provides a method for erasing a trapping nonvolatile memory cell. An embodiment of the method according to the invention comprises the steps of applying a voltage between the gate and the semiconductor substrate including the source and the drain, where the voltage is large enough to form a tunnel so as to induce an electric current along a path from the semiconductor substrate having the source and the drain to the trapping layer. Moreover, the voltage can be reversely added so as to form a tunnel to induce an electric current along a path from the gate to the trapping layer.
The invention further provides a method for erasing a trapping nonvolatile memory cell by adding a series of pulses. According to an embodiment of the method according to the invention, a series of bipolar pulses are input into a selected electrode of the drain and the source while another electrode of the drain and source is being floated. Each of the pulse includes a second voltage and a third voltage smaller than the second voltage, where the third voltage is enough to cause electrons to be drawn out from the selected electrode. Moreover, the second voltage is enough to cut off the electron current flow from the selected electrode to the semiconductor substrate and to induce the electrons to inject into the trapping layer. In addition, the pulses can be input from the source and drain synchronously, or directly input from the semiconductor substrate.
The invention further provides a method for erasing a trapping nonvolatile memory cell. An embodiment of the method according to the invention comprises the steps of making an N well enclosing the semiconductor substrate, grounding or floating the drain and the source, and applying voltages to the gate, the P well and the N well, thereby causing an electron current path to induce electrons to flow from the N well to the P well and then be injected into the trapping layer through the first isolating layer. Moreover, instead of using an N well, a N+ injector can be formed in the semiconductor substrate.